Fan-out wafer level packaging (“FO-WLP”) processes may involve the formation of redistribution layers over a molded package body in which one or more semiconductor die are embedded. The redistribution layers provide electrical interconnection between bond pads located on the semiconductor die and a contact array, such as a ball grid array, formed over a surface of the completed die package. The redistribution layers allow the bond pads to have a relatively tight pad-to-pad spacing and pitch, while still providing a comparably large surface area over which the contact array can be distributed or fanned-out. To produce the redistribution layers, one or more layers of dielectric material are initially deposited over the die and cover the bond pads. In one conventional approach, a separate via is etched through the dielectric layer to expose a portion of each contact pad, metal plugs or other conductors are then formed in each via to provide ohmic contact with the contact pad, and a metal trace or interconnect line is formed in contact with each conductor. More recently, an improved approach has been introduced wherein a single elongated via referred to as a “trench via” is formed to simultaneously expose multiple bond pads, which may be arranged in a row, through the overlying dielectric. Interconnect lines are then formed extending into the trench via and directly contact the bond pads exposed thereby. Such an approach allows the production of high density, fine pitch interconnect structures in a highly efficient and repeatable manner.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.